The TLC5540 is a high-speed, 8-bit analog-to-digital converter (ADC) that converts at sampling rates up to 40 megasamples per second (MSPS). Using a semiflash architecture and CMOS process, the TLC5540 is able to convert at high speeds while still maintaining low power consumption and cost. The analog input bandwidth of 75 MHz (typ) makes this device an excellent choice for undersampling applications. Internal resistors are provided to generate 2-V full-scale reference voltages from a 5-V supply, thereby reducing external components.

The digital outputs can be placed in a high impedance mode. The TLC5540 requires only a single 5-V supply for operation.

The AD5697R, a member of the nanoDAC+™ family, is a low power, dual, 12-bit buffered voltage output digital-to-analog converter (DAC). The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The AD5697R operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.

The AD5697R also incorporates a power-on reset circuit and a RSTSEL pin that ensure that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. It contains a per channel power-down feature that reduces the current consumption of the device to 4 µA at 3 V while in power-down mode.

The AD5697R uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.

The ISLA214P50IRZ is a 14-bit Analog-to-digital Converter (ADC) designed with Intersils proprietary FemtoCharge™ technology on a standard CMOS process. The device utilizes two time-interleaved 250MSPS unit ADC to achieve the ultimate sample rate of 500MSPS. A single 500MHz conversion clock is presented to the converter and all interleave clocking is managed internally. The proprietary Intersil Interleave Engine performs automatic correction of offset, gain and sample time mismatches between the units ADC to optimize performance. A serial peripheral interface port allows for extensive configurability of the A/D. The SPI also controls the interleave correction circuitry, allowing the system to issue offline and continuous calibration commands as well as configure many dynamic parameters.

• Automatic fine interleave correction calibration
• Clock duty cycle stabilizer
• Programmable built-in test patterns
• SPI programmable fine gain and offset control
• Support for multiple ADC synchronization
• Optimized output timing
• Nap and sleep modes
• Data output clock
• DDR LVDS-compatible or LVCMOS outputs
• Selectable clock divider