The SN74HC112N is a dual negative-edge-triggered J-K Flip-flop with clear and preset. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop performs as toggle flip-flop by tying J and K high.

• Outputs can drive up to 10 LSTTL loads
• 13ns Typical tpd
• ±4mA Output drive at 5V
• 1µA Maximum low input current
• 40µA Maximum low power consumption

The CD74HC74E is a high speed CMOS logic dual positive-edge-triggered D-type Flip-flop with set and reset. The HC74 utilizes silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. This flip-flop has independent DATA, SET\, RESET\ and CLOCK inputs and Q and Q\ outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. SET\ and RESET\ are independent of the clock and are accomplished by a low level at the appropriate input.

• Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
• Asynchronous reset
• Complementary outputs
• Buffered inputs
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL logic ICs
• ±20mA DC input/output diode current
• ±25mA DC drain current

The SN74LVC1G32DBVR is a Single 2-input Positive-OR Gate, designed for 1.65 to 5.5V VCC operation. The SN74LVC1G32DBVR device performs the Boolean function Y = A + B or Y = A\ + B\ in positive logic. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range. ESD protection exceeds JESD 22, 2000V human body model (A114-A), 200V machine model (A115-A) and 1000V charged-device model (C101).

• Supports 5V VCC operation
• Inputs accept voltages to 5.5V
• Supports down translation to VCC
• Maximum TPD of 3.6ns at 3.3V
• Low power consumption, 10µA maximum ICC
• ±24mA Output drive at 3.3V
• Ioff supports live insertion, partial-power-down mode and back-drive protection
• Latch-up performance exceeds 100mA per JESD 78, class II
• Green product and no Sb/Br