The SN74LVC1G332DBVR is a single 3-input positive-OR Gate. The device performs the Boolean function in Y = A + B + C or (A\ • B\ • C\)\ positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• ±24mA Output drive at 3.3V
• 10µA Maximum ICC low power consumption
• Inputs accept voltages to 5.5V
• Maximum tpd of 4.5ns at 3.3V
• Ioff supports live insertion, partial power down mode and back drive protection
• Supports down translation to VCC
• ESD protection exceeds JESD 22
• Latch-up performance exceeds 100mA per JESD 78, Class II
• Green product and no Sb/Br

The SN74LVC1G74DCTR is a single positive-edge-triggered D-type Flip-flop is designed for 1.65 to 5.5V VCC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Supports down translation to VCC
• ±24mA Output drive at 3.3V
• Ioff Supports live insertion, partial-power-down mode and back-drive protection
• Latch-up performance exceeds 100mA per JESD 78, class II
• Green product and no Sb/Br

The CD74HC74E is a high speed CMOS logic dual positive-edge-triggered D-type Flip-flop with set and reset. The HC74 utilizes silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. This flip-flop has independent DATA, SET\, RESET\ and CLOCK inputs and Q and Q\ outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. SET\ and RESET\ are independent of the clock and are accomplished by a low level at the appropriate input.

• Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
• Asynchronous reset
• Complementary outputs
• Buffered inputs
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL logic ICs
• ±20mA DC input/output diode current
• ±25mA DC drain current