| REACH SVHC Compliance | No SVHC |
|---|---|
| Mounting Style | Through Hole |
| Number of Bits | 2 |
| Number of Circuits | 2 |
| Lead-Free Status | Lead Free |
| Operating Temperature | -40.0 °C to 85.0 °C |
| Case/Package | PDIP |
| Frequency | 24.0 MHz |
| Output Current | 5.20 mA |
| Number of Pins | 16 |
| Propagation Delay Max (tpd) | 26.0 ns |
| RoHS | Compliant |
| Supply Voltage (DC) | 2.00 V to 6.00 V |
| Polarity | Inverting, Non-Inverting |
| Output Current Drive | -1.00 mA |
| Voltage Nodes | 2.00 V, 5.00 V, 6.00 V |
| Packaging | Tube, Rail |
| Lifecycle Status | Active |
Logic
| Manufacturer | Texas Instruments |
|---|---|
| Manufacturer Part Number | SN74HC112N |
| Description | IC, J-K Flip-Flop Dual PDIP-16 |
| Stock Code | W007161 |
| Download |  Technical Datasheet |
The SN74HC112N is a dual negative-edge-triggered J-K Flip-flop with clear and preset. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop performs as toggle flip-flop by tying J and K high.
- Outputs can drive up to 10 LSTTL loads
- 13ns Typical tpd
- ±4mA Output drive at 5V
- 1µA Maximum low input current
- 40µA Maximum low power consumption
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