The SN74LVC1T45DCKT is a single-bit non-inverting Bus Transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8, 2.5, 3.3 and 5V voltage nodes. It is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. It is designed so that the DIR input is powered by VCCA.

• Fully configurable dual-rail design allows each port to operate over 1.65 to 5.5V power supply range
• VCC Isolation Feature, If Either VCC Input Is at GND, Both Ports Are in High-Impedance State
• DIR Input Circuit Referenced to VCCA
• Low-power Consumption, 4µA Maximum ICC
• ±24mA Output Drive at 3.3V
• Ioff Supports Partial-power-down Mode Operation
• 420Mbps(3.3 to 5V Translation) 210Mbps(Translate to 3.3V), 75Mbps (Translate to 1.8V) max data rates
• Latch-up Performance Exceeds 100mA Per JESD 78, Class II
• Green Product, No Sb/Br

The SN74LVC1G11DBVR is a Single 3-input Positive-AND Gate performs the Boolean function in positive logic. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ESD protection exceeds JESD 22, 2000V human-body model (A114-A), 200V machine model (A115-A) and 1000V charged-device model (C101).

• Supports 5V VCC operation
• Inputs accept voltages to 5.5V
• Maximum TPD of 4.1ns at 3.3V
• Low power consumption, 10µA maximum ICC
• ±24mA Output drive at 3.3V
• Ioff supports partial power-down mode operation
• Latch-up performance exceeds 100mA per JESD 78, class II
• Green product and no Sb/Br

The CD74HC74E is a high speed CMOS logic dual positive-edge-triggered D-type Flip-flop with set and reset. The HC74 utilizes silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. This flip-flop has independent DATA, SET\, RESET\ and CLOCK inputs and Q and Q\ outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. SET\ and RESET\ are independent of the clock and are accomplished by a low level at the appropriate input.

• Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
• Asynchronous reset
• Complementary outputs
• Buffered inputs
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL logic ICs
• ±20mA DC input/output diode current
• ±25mA DC drain current