The ISLA214P50IRZ is a 14-bit Analog-to-digital Converter (ADC) designed with Intersils proprietary FemtoCharge™ technology on a standard CMOS process. The device utilizes two time-interleaved 250MSPS unit ADC to achieve the ultimate sample rate of 500MSPS. A single 500MHz conversion clock is presented to the converter and all interleave clocking is managed internally. The proprietary Intersil Interleave Engine performs automatic correction of offset, gain and sample time mismatches between the units ADC to optimize performance. A serial peripheral interface port allows for extensive configurability of the A/D. The SPI also controls the interleave correction circuitry, allowing the system to issue offline and continuous calibration commands as well as configure many dynamic parameters.

• Automatic fine interleave correction calibration
• Clock duty cycle stabilizer
• Programmable built-in test patterns
• SPI programmable fine gain and offset control
• Support for multiple ADC synchronization
• Optimized output timing
• Nap and sleep modes
• Data output clock
• DDR LVDS-compatible or LVCMOS outputs
• Selectable clock divider

The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9548 generates an output clock synchronized to one of up to four differential or eight single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9548 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry.

The AD9548 operates over an industrial temperature range of −40°C to +85°C.

• Supports Stratum 2 stability in holdover mode
• Supports reference switchover with phase build-out
• Supports hitless reference switchover
• Auto/manual holdover and reference switchover
• 4 pairs of reference input pins with each pair configurable as a single differential input or as 2 independent singleended inputs
• Input reference frequencies from 1 Hz to 750 MHz
• Reference validation and frequency monitoring (1 ppm)
• Programmable input reference switchover priority
• 30-bit programmable input reference divider
• 4 pairs of clock output pins with each pair configurable as a
• single differential LVDS/LVPECL output or as 2 singleended CMOS outputs
• Output frequencies up to 450 MHz
• 30-bit integer and 10-bit fractional programmable feedback divider
• Programmable digital loop filter covering loop bandwidths from 0.001 Hz to 100 kHz
• Optional low noise LC-VCO system clock multiplier
• Optional crystal resonator for system clock input
• On-chip EEPROM to store multiple power-up profiles
• Software controlled power-down
• 88-lead LFCSP package