The ADS1015IDGST is a Precision Analogue-to-digital Converter (ADC) with 12 bits of resolution. Designed with precision, power and ease of implementation in mind. It features an onboard reference and oscillator. Data are transferred via an I²C-compatible serial interface, four I²C slave addresses can be selected. It operates from a single power supply ranging from 2.0 to 5.5V. It can perform conversions at rates up to 3300 samples per second (SPS). An onboard PGA is available, that offers input ranges from the supply to as low as ±256mV, allowing both large and small signals to be measured with high resolution. Also features an input multiplexer (MUX) that provides two differential or four single-ended inputs. It operates either in continuous conversion mode or a single-shot mode that automatically powers down after a conversion and greatly reduces current consumption during idle periods.

• Low current consumption 128SPS to 3.3kSPS Programmable data rate
• Internal low-drift voltage reference
• Internal oscillator
• Internal PGA
• I²C Interface, pin-selectable addresses
• Four single-ended or two differential inputs
• Programmable comparator

The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9548 generates an output clock synchronized to one of up to four differential or eight single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9548 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry.

The AD9548 operates over an industrial temperature range of −40°C to +85°C.

• Supports Stratum 2 stability in holdover mode
• Supports reference switchover with phase build-out
• Supports hitless reference switchover
• Auto/manual holdover and reference switchover
• 4 pairs of reference input pins with each pair configurable as a single differential input or as 2 independent singleended inputs
• Input reference frequencies from 1 Hz to 750 MHz
• Reference validation and frequency monitoring (1 ppm)
• Programmable input reference switchover priority
• 30-bit programmable input reference divider
• 4 pairs of clock output pins with each pair configurable as a
• single differential LVDS/LVPECL output or as 2 singleended CMOS outputs
• Output frequencies up to 450 MHz
• 30-bit integer and 10-bit fractional programmable feedback divider
• Programmable digital loop filter covering loop bandwidths from 0.001 Hz to 100 kHz
• Optional low noise LC-VCO system clock multiplier
• Optional crystal resonator for system clock input
• On-chip EEPROM to store multiple power-up profiles
• Software controlled power-down
• 88-lead LFCSP package