| Number of Pins | 88 |
|---|---|
| Packaging | Tray |
| RoHS | Compliant |
| Supply Current | 190 mA |
| Supply Voltage (DC) | 1.89 V (max), 3.46 V (max), 1.71 V (min) |
| Operating Temperature | -40.0 °C (min) |
| Mounting Style | Surface Mount |
| Frequency | 1.00 GHz |
| Input Current | 24.0 mA |
| Lead-Free Status | Contains Lead |
| Lifecycle Status | Active |
Data & Signal Conversion
| Manufacturer | Analog Devices |
|---|---|
| Manufacturer Part Number | AD9548BCPZ |
| Description | Clock IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| Stock Code | W006838 |
| Download |  Technical Datasheet |
The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9548 generates an output clock synchronized to one of up to four differential or eight single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9548 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry.
The AD9548 operates over an industrial temperature range of −40°C to +85°C.
- Supports Stratum 2 stability in holdover mode
- Supports reference switchover with phase build-out
- Supports hitless reference switchover
- Auto/manual holdover and reference switchover
- 4 pairs of reference input pins with each pair configurable as a single differential input or as 2 independent singleended inputs
- Input reference frequencies from 1 Hz to 750 MHz
- Reference validation and frequency monitoring (1 ppm)
- Programmable input reference switchover priority
- 30-bit programmable input reference divider
- 4 pairs of clock output pins with each pair configurable as a
- single differential LVDS/LVPECL output or as 2 singleended CMOS outputs
- Output frequencies up to 450 MHz
- 30-bit integer and 10-bit fractional programmable feedback divider
- Programmable digital loop filter covering loop bandwidths from 0.001 Hz to 100 kHz
- Optional low noise LC-VCO system clock multiplier
- Optional crystal resonator for system clock input
- On-chip EEPROM to store multiple power-up profiles
- Software controlled power-down
- 88-lead LFCSP package
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