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Logic
Texas Instruments SN74LVC1G08DBVR
The SN74LVC1G08DBVR is a single 2-input positive-AND gate IC, designed for 1.65 to 5.5V VCC operation. The device performs the Boolean function or in positive logic. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.
- Supports 5V VCC Operation
- Input Accepts Voltage to 5.5V
- Provides Down Translation to VCC
- 3.6ns at 3.3V Maximum Propagation Delay Time
- Low-power Consumption, 10µA Maximum ICC
- ±24mA Output Drive at 3.3V
- Ioff Supports Live Insertion, Partial-power-down Mode and Back Drive Protection
- Latch-up Performance Exceeds 100mA Per JESD 78, Class II
- Green Product, No Sb/Br
SKU: W006355 -
Logic
Texas Instruments SA555D
The SA555D is a Precision Timer capable of producing accurate time delay or oscillation. In the mono-stable mode of operation the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are 2/3rd and 1/3rd respectively of VCC. When the trigger input falls below the trigger level the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. When RESET goes low the flip-flop is reset and the output goes low. When the output is low a low-impedance path is provided between discharge and ground.
- Timing from microseconds to hours
- Adjustable duty cycle
- TTL-compatible output can sink or source up to 200mA
- Green product and no Sb/Br
SKU: W014004 -
Logic
Texas Instruments SN74HC112N
The SN74HC112N is a dual negative-edge-triggered J-K Flip-flop with clear and preset. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop performs as toggle flip-flop by tying J and K high.
- Outputs can drive up to 10 LSTTL loads
- 13ns Typical tpd
- ±4mA Output drive at 5V
- 1µA Maximum low input current
- 40µA Maximum low power consumption
SKU: W007161
