|Number of Pins||
|REACH SVHC Compliance||
|Supply Voltage (DC)||
16.0 V (max), 4.50 V (min)
15.0 mA (max)
Cut Tape (CT)
-40.0 °C to 85.0 °C
|Manufacturer Part Number||SA555D|
|Description||BIPOLAR TIMER SINGLE GEN PURPOSE|
The SA555D is a Precision Timer capable of producing accurate time delay or oscillation. In the mono-stable mode of operation the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are 2/3rd and 1/3rd respectively of VCC. When the trigger input falls below the trigger level the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. When RESET goes low the flip-flop is reset and the output goes low. When the output is low a low-impedance path is provided between discharge and ground.
- Timing from microseconds to hours
- Adjustable duty cycle
- TTL-compatible output can sink or source up to 200mA
- Green product and no Sb/Br
Texas Instruments SN74LVC1G74DCTR0 out of 5(0)
The SN74LVC1G74DCTR is a single positive-edge-triggered D-type Flip-flop is designed for 1.65 to 5.5V VCC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
- Supports down translation to VCC
- ±24mA Output drive at 3.3V
- Ioff Supports live insertion, partial-power-down mode and back-drive protection
- Latch-up performance exceeds 100mA per JESD 78, class II
- Green product and no Sb/Br
Texas Instruments SN74HC112N0 out of 5(0)
The SN74HC112N is a dual negative-edge-triggered J-K Flip-flop with clear and preset. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop performs as toggle flip-flop by tying J and K high.
- Outputs can drive up to 10 LSTTL loads
- 13ns Typical tpd
- ±4mA Output drive at 5V
- 1µA Maximum low input current
- 40µA Maximum low power consumption
Texas Instruments SN74HC595N0 out of 5(0)
The SN74HC595N device contain an 8 bit serial in, parallel out shift register that feeds an 8 bit D type storage register. The storage register has parallel 3 state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
- 8 bit serial-in, parallel-out shift
- Wide operating voltage range of 2V to 6V
- High current 3 state outputs can drive up To 15 LSTTL loads
- Low power consumption: 80µA max.
- ±6-mA output drive at 5V
- Low input current: 1µA max.
- Shift register has direct clear
Texas Instruments TXB0104PWR0 out of 5(0)
The TXB0104PWR is a 4-bit non-inverting translator IC uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.2, 1.5, 1.8, 2.5, 3.3V and 5V voltage nodes. VCCA should not exceed VCCB. When the output-enable (OE) input is low, all outputs are placed in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pull-down resistor, the minimum value of the resistor is determined by the current-sourcing capability of the driver. It is designed so that the OE input circuit is supplied by VCCA.
- 1.2 to 3.6V on A Port and 1.65 to 5.5V on B Port (VCCA<=VCCB)
- VCC Isolation Feature – If Either VCC Input Is at GND, All Outputs are in High-Impedance State
- OE Input Circuit Referenced to VCCA
- Low-power Consumption, 5µA Maximum ICC
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-up Performance Exceeds 100mA Per JESD 78, Class II
- Green Product, No Sb/Br