|REACH SVHC Compliance||
|Number of Bits||
|Number of Circuits||
-40.0 °C to 85.0 °C
|Number of Pins||
|Propagation Delay Max (tpd)||
|Supply Voltage (DC)||
2.00 V to 6.00 V
|Output Current Drive||
2.00 V, 5.00 V, 6.00 V
|Manufacturer Part Number||SN74HC112N|
|Description||IC, J-K Flip-Flop Dual PDIP-16|
The SN74HC112N is a dual negative-edge-triggered J-K Flip-flop with clear and preset. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop performs as toggle flip-flop by tying J and K high.
- Outputs can drive up to 10 LSTTL loads
- 13ns Typical tpd
- ±4mA Output drive at 5V
- 1µA Maximum low input current
- 40µA Maximum low power consumption
CD74HC244E IC BUFF/DVR TRI-ST DUAL 20DIP0 out of 5(0)
The CD74HC244E is an inverting three-state Buffer has two active-low output enables. The CD74HC244 is high speed CMOS logic buffer has two active-low output enables. It offers high noise immunity of NIL = 30%, NIH = 30% of VCC at VCC = 5V and AC types feature 1.5 to 5.5V operation and balanced noise immunity at 30% of the supply.
- Buffered inputs
- High-current bus driver outputs
- Balanced propagation delay and transition times
- Significant power reduction compared to LSTTL logic ICs
- Standard outputs – 10 LSTTL loads
- Bus driver outputs – 15 LSTTL loads
Texas Instruments SN74HC595N0 out of 5(0)
The SN74HC595N device contain an 8 bit serial in, parallel out shift register that feeds an 8 bit D type storage register. The storage register has parallel 3 state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
- 8 bit serial-in, parallel-out shift
- Wide operating voltage range of 2V to 6V
- High current 3 state outputs can drive up To 15 LSTTL loads
- Low power consumption: 80µA max.
- ±6-mA output drive at 5V
- Low input current: 1µA max.
- Shift register has direct clear
Texas Instruments SN74LVC1G32DBVR0 out of 5(0)
The SN74LVC1G32DBVR is a Single 2-input Positive-OR Gate, designed for 1.65 to 5.5V VCC operation. The SN74LVC1G32DBVR device performs the Boolean function Y = A + B or Y = A\ + B\ in positive logic. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range. ESD protection exceeds JESD 22, 2000V human body model (A114-A), 200V machine model (A115-A) and 1000V charged-device model (C101).
- Supports 5V VCC operation
- Inputs accept voltages to 5.5V
- Supports down translation to VCC
- Maximum TPD of 3.6ns at 3.3V
- Low power consumption, 10µA maximum ICC
- ±24mA Output drive at 3.3V
- Ioff supports live insertion, partial-power-down mode and back-drive protection
- Latch-up performance exceeds 100mA per JESD 78, class II
- Green product and no Sb/Br
Texas Instruments SA555D0 out of 5(0)
The SA555D is a Precision Timer capable of producing accurate time delay or oscillation. In the mono-stable mode of operation the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are 2/3rd and 1/3rd respectively of VCC. When the trigger input falls below the trigger level the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. When RESET goes low the flip-flop is reset and the output goes low. When the output is low a low-impedance path is provided between discharge and ground.
- Timing from microseconds to hours
- Adjustable duty cycle
- TTL-compatible output can sink or source up to 200mA
- Green product and no Sb/Br