| REACH SVHC Compliance | No SVHC |
|---|---|
| Number of Bits | 1 |
| Number of Circuits | 1 |
| Number of Gates | 1 |
| Lifecycle Status | Active |
| Operating Temperature | -40.0 °C to 85.0 °C |
| Case/Package | SOT-23 |
| Lead-Free Status | Lead Free |
| Output Current | 32.0 mA |
| Number of Pins | 5 |
| Quiescent Current | 10.0 µA (max) |
| RoHS | Compliant |
| Supply Voltage (DC) | 1.65 V to 5.50 V |
| Propagation Delay Max (tpd) | 4.00 ns |
| Output Current Drive | -1.00 mA |
| Voltage Nodes | 1.80 V, 5.00 V, 3.30 V, 2.50 V |
| Packaging | Cut Tape (CT), Reel, Tape & Reel (TR) |
| Mounting Style | Surface Mount |
Logic
| Manufacturer | Texas Instruments |
|---|---|
| Manufacturer Part Number | SN74LVC1G32DBVR |
| Description | IC GATE OR 1CH 2-INP SOT-23-5 |
| Stock Code | W006357 |
| Download |  Technical Datasheet |
The SN74LVC1G32DBVR is a Single 2-input Positive-OR Gate, designed for 1.65 to 5.5V VCC operation. The SN74LVC1G32DBVR device performs the Boolean function Y = A + B or Y = A\ + B\ in positive logic. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range. ESD protection exceeds JESD 22, 2000V human body model (A114-A), 200V machine model (A115-A) and 1000V charged-device model (C101).
- Supports 5V VCC operation
- Inputs accept voltages to 5.5V
- Supports down translation to VCC
- Maximum TPD of 3.6ns at 3.3V
- Low power consumption, 10µA maximum ICC
- ±24mA Output drive at 3.3V
- Ioff supports live insertion, partial-power-down mode and back-drive protection
- Latch-up performance exceeds 100mA per JESD 78, class II
- Green product and no Sb/Br
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Logic
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The SN74LVC1G74DCTR is a single positive-edge-triggered D-type Flip-flop is designed for 1.65 to 5.5V VCC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
- Supports down translation to VCC
- ±24mA Output drive at 3.3V
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Logic
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The SN74LVC1G332DBVR is a single 3-input positive-OR Gate. The device performs the Boolean function in Y = A + B + C or (A\ • B\ • C\)\ positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
- ±24mA Output drive at 3.3V
- 10µA Maximum ICC low power consumption
- Inputs accept voltages to 5.5V
- Maximum tpd of 4.5ns at 3.3V
- Ioff supports live insertion, partial power down mode and back drive protection
- Supports down translation to VCC
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Logic
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The 74HC74N is a dual D-type positive-edge-triggered Flip-flop with clear and preset. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D-input can be changed without affecting the levels at the outputs.
- Wide operating voltage range
- Outputs can drive up to 10 LSTTL loads
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Logic
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The SN74HC595N device contain an 8 bit serial in, parallel out shift register that feeds an 8 bit D type storage register. The storage register has parallel 3 state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
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- Shift register has direct clear
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