The SN74LVC1G74DCTR is a single positive-edge-triggered D-type Flip-flop is designed for 1.65 to 5.5V VCC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Supports down translation to VCC
• ±24mA Output drive at 3.3V
• Ioff Supports live insertion, partial-power-down mode and back-drive protection
• Latch-up performance exceeds 100mA per JESD 78, class II
• Green product and no Sb/Br

The SN74LVC1T45DCKT is a single-bit non-inverting Bus Transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8, 2.5, 3.3 and 5V voltage nodes. It is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. It is designed so that the DIR input is powered by VCCA.

• Fully configurable dual-rail design allows each port to operate over 1.65 to 5.5V power supply range
• VCC Isolation Feature, If Either VCC Input Is at GND, Both Ports Are in High-Impedance State
• DIR Input Circuit Referenced to VCCA
• Low-power Consumption, 4µA Maximum ICC
• ±24mA Output Drive at 3.3V
• Ioff Supports Partial-power-down Mode Operation
• 420Mbps(3.3 to 5V Translation) 210Mbps(Translate to 3.3V), 75Mbps (Translate to 1.8V) max data rates
• Latch-up Performance Exceeds 100mA Per JESD 78, Class II
• Green Product, No Sb/Br