The SN74LVC1G04DBVR is a single inverter gate IC, designed for 1.65 to 5.5V VCC operation. The device performs the Boolean function Y = A. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

• Supports 5V VCC Operation
• Input Accepts Voltage up to 5.5V Allowing Down Translation to VCC
• 3.3ns at 3.3V Maximum Propagation Delay Time
• Low-power Consumption, 10µA Maximum ICC
• ±24mA Output Drive at 3.3V
• Ioff Supports Live-insertion, Partial-power-down Mode and Back-drive Protection
• Latch-up Performance Exceeds 100mA Per JESD 78, Class II
• Green Product, No Sb/Br

The SN74HC112N is a dual negative-edge-triggered J-K Flip-flop with clear and preset. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop performs as toggle flip-flop by tying J and K high.

• Outputs can drive up to 10 LSTTL loads
• 13ns Typical tpd
• ±4mA Output drive at 5V
• 1µA Maximum low input current
• 40µA Maximum low power consumption