| Propagation Delay Max (tpd) | 4.40 ns |
|---|---|
| Packaging | Cut Tape (CT), Tape & Reel (TR) |
| Output Current | 32.0 mA, 50.0 mA |
| REACH SVHC Compliance | No SVHC |
| RoHS | Compliant |
| Number of Pins | 8 |
| Supply Voltage (DC) | 5.50 V (max), 1.65 V (min) |
| Operating Temperature | -40.0 °C (min) |
| Number of Gates | 2 |
| Frequency | 200 MHz |
| Case/Package | SSOP |
| Lifecycle Status | Active |
| Number of Bits | 1 |
| Mounting Style | Surface Mount |
| Lead-Free Status | Lead Free |
Logic
| Manufacturer | Texas Instruments |
|---|---|
| Manufacturer Part Number | SN74LVC1G74DCTR |
| Description | Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset 8-SM8 -40 to 125 |
| Stock Code | W008690 |
| Download |  Technical Datasheet |
The SN74LVC1G74DCTR is a single positive-edge-triggered D-type Flip-flop is designed for 1.65 to 5.5V VCC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
- Supports down translation to VCC
- ±24mA Output drive at 3.3V
- Ioff Supports live insertion, partial-power-down mode and back-drive protection
- Latch-up performance exceeds 100mA per JESD 78, class II
- Green product and no Sb/Br
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