| Case/Package | FCBGA |
|---|---|
| Mounting Style | Surface Mount |
| Brand | Xilinx Inc. |
| Series | Virtex-4 SX |
| Number of LABs/CLBs | 2560 |
| Number of Logic Elements/Cells | 23040 |
| Total RAM Bits | 2359296 |
| Number of I/O | 320 |
| Voltage - Supply | 1.14V ~ 1.26V |
| Package / Case | 668-BBGA, FCBGA |
| Supplier Device Package | 668-FCBGA (27×27) |
FPGA & Microcontrollers
| Manufacturer | Xilinx |
|---|---|
| Manufacturer Part Number | XC4VSX25-10FFG668I |
| Description | IC FPGA 320 I/O 668FCBGA |
| Stock Code | W004339 |
| Download |  Technical Datasheet |
Combining Advanced Silicon Modular Block (ASMBL™) architecture with a wide variety of flexible features, the Virtex®-4 family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC technology. Virtex-4 FPGAs comprise three platform families LX, FX, and SX offering multiple feature choices and combinations to address all complex applications. The wide array of Virtex-4 FPGA hard-IP core blocks includes the PowerPC® processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4 FPGA building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a state-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology.
- Virtex-4 LX: High-performance logic applications solution
- Virtex-4 SX: High-performance solution for digital signal processing (DSP) applications
- Virtex-4 FX: High-performance, full-featured solution for embedded platform applications
- Xesium™ Clock Technology
- Digital clock manager (DCM) blocks
- Additional phase-matched clock dividers (PMCD)
- Differential global clocks
- XtremeDSP™ Slice
- 18 x 18, two’s complement, signed Multiplier
- Optional pipeline stages
- Built-in Accumulator (48-bit) and Adder/Subtracter
- Smart RAM Memory Hierarchy
- Distributed RAM
- Dual-port 18-Kbit RAM blocks
- Optional pipeline stages
- Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals
- High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.
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