The Spartan®-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates.

The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment.

The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.

XC3S500E-4PQ208I FPGA Spartan-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP

• Very low cost, high-performance logic solution for high-volume, consumer-oriented applications
• Proven advanced 90-nanometer process technology
• Multi-voltage, multi-standard SelectIO™ interface pins
• Up to 376 I/O pins or 156 differential signal pairs
• LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards
• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
• 622+ Mb/s data transfer rate per I/O
• True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O
• Enhanced Double Data Rate (DDR) support
• DDR SDRAM support up to 333 Mb/s
• Densities up to 33,192 logic cells, including optional shift register or distributed RAM support
• Efficient wide multiplexers, wide logic
• Enhanced 18 x 18 multipliers with optional pipeline
• IEEE 1149.1/1532 JTAG programming/debug port
• Hierarchical SelectRAM™ memory architecture
• Up to 648 Kbits of fast block RAM
• Up to 231 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)
• Frequency synthesis, multiplication, division
• Wide frequency range (5 MHz to over 300 MHz)
• Eight global clocks plus eight additional clocks per each half of device, plus abundant low-skew routing
• Low-cost, space-saving SPI serial Flash PROM
• x8 or x8/x16 parallel NOR Flash PROM
• Low-cost Xilinx® Platform Flash with JTAG
• Complete Xilinx ISE® and WebPACK™ software
• MicroBlaze™ and PicoBlazeembedded processor cores
• Fully compliant 32-/64-bit 33 MHz PCI support (66 MHz in some devices)

Artix®-7 FPGAs are available in -3, -2, -1, -1LI, and -2L speed grades, with -3 having the highest performance. The Artix-7 FPGAs predominantly operate at a 1.0V core voltage. The -1LI and -2L devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -1 and -2 devices, respectively. The -1LI devices operate only at VCCINT = VCCBRAM = 0.95V and have the same speed specifications as the -1 speed grade. The -2L devices can operate at either of two VCCINT voltages, 0.9V and 1.0V and are screened for lower maximum static power. When operated at VCCINT = 1.0V, the speed specification of a -2L device is the same as the -2 speed grade. When operated at VCCINT = 0.9V, the -2L static and dynamic power is reduced.

Artix-7 FPGA DC and AC characteristics are specified in commercial, extended, industrial, expanded (-1Q), and military (-1M) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1M speed grade military device are the same as for a -1C speed grade commercial device). However, only selected speed grades and/or devices are available in each temperature range. For example, -1M is only available in the defense-grade Artix-7Q family and -1Q is only available in XA Artix-7 FPGAs.

All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications.

Combining Advanced Silicon Modular Block (ASMBL™) architecture with a wide variety of flexible features, the Virtex®-4 family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC technology. Virtex-4 FPGAs comprise three platform families LX, FX, and SX offering multiple feature choices and combinations to address all complex applications. The wide array of Virtex-4 FPGA hard-IP core blocks includes the PowerPC® processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4 FPGA building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a state-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology.

• Virtex-4 LX: High-performance logic applications solution
• Virtex-4 SX: High-performance solution for digital signal processing (DSP) applications
• Virtex-4 FX: High-performance, full-featured solution for embedded platform applications
• Xesium™ Clock Technology
• Digital clock manager (DCM) blocks
• Additional phase-matched clock dividers (PMCD)
• Differential global clocks
• XtremeDSP™ Slice
• 18 x 18, two’s complement, signed Multiplier
• Optional pipeline stages
• Built-in Accumulator (48-bit) and Adder/Subtracter
• Smart RAM Memory Hierarchy
• Distributed RAM
• Dual-port 18-Kbit RAM blocks
• Optional pipeline stages
• Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals
• High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.