Logic

The 74HC74N is a dual D-type positive-edge-triggered Flip-flop with clear and preset. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D-input can be changed without affecting the levels at the outputs.

• Wide operating voltage range
• Outputs can drive up to 10 LSTTL loads
• Low power consumption
• 15ns Typical TPD
• ±4mA Output drive at 5V

The CD74HC74E is a high speed CMOS logic dual positive-edge-triggered D-type Flip-flop with set and reset. The HC74 utilizes silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. This flip-flop has independent DATA, SET\, RESET\ and CLOCK inputs and Q and Q\ outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. SET\ and RESET\ are independent of the clock and are accomplished by a low level at the appropriate input.

• Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
• Asynchronous reset
• Complementary outputs
• Buffered inputs
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL logic ICs
• ±20mA DC input/output diode current
• ±25mA DC drain current

The SN74HC595N device contain an 8 bit serial in, parallel out shift register that feeds an 8 bit D type storage register. The storage register has parallel 3 state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

• 8 bit serial-in, parallel-out shift
• Wide operating voltage range of 2V to 6V
• High current 3 state outputs can drive up To 15 LSTTL loads
• Low power consumption: 80µA max.
• ±6-mA output drive at 5V
• Low input current: 1µA max.
• Shift register has direct clear

The SN74LVC1G00DBVR is a Single 2-input Positive-NAND Gate, designed for 1.65 to 5.5V VCC operation. The SN74LVC1G00DBVR performs the Boolean function Y = A x B or Y = A + B in positive logic. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range. ESD protection exceeds JESD 22, 2000V human-body model (A114-A) and 1000V charged-device model (C101).

• Supports 5V VCC operation
• Inputs accept voltages to 5.5V
• Provides down translation to VCC
• Maximum TPD of 3.8ns at 3.3V
• Low power consumption, 10µA maximum ICC
• ±24mA Output drive at 3.3V
• Ioff supports live insertion, partial power-down mode operation and back-drive protection
• Latch-up performance exceeds 100mA per JESD 78, class II
• Green product and no Sb/Br

The SN74LVC1G04DBVR is a single inverter gate IC, designed for 1.65 to 5.5V VCC operation. The device performs the Boolean function Y = A. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

• Supports 5V VCC Operation
• Input Accepts Voltage up to 5.5V Allowing Down Translation to VCC
• 3.3ns at 3.3V Maximum Propagation Delay Time
• Low-power Consumption, 10µA Maximum ICC
• ±24mA Output Drive at 3.3V
• Ioff Supports Live-insertion, Partial-power-down Mode and Back-drive Protection
• Latch-up Performance Exceeds 100mA Per JESD 78, Class II
• Green Product, No Sb/Br

The SN74LVC1G32DBVR is a Single 2-input Positive-OR Gate, designed for 1.65 to 5.5V VCC operation. The SN74LVC1G32DBVR device performs the Boolean function Y = A + B or Y = A\ + B\ in positive logic. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range. ESD protection exceeds JESD 22, 2000V human body model (A114-A), 200V machine model (A115-A) and 1000V charged-device model (C101).

• Supports 5V VCC operation
• Inputs accept voltages to 5.5V
• Supports down translation to VCC
• Maximum TPD of 3.6ns at 3.3V
• Low power consumption, 10µA maximum ICC
• ±24mA Output drive at 3.3V
• Ioff supports live insertion, partial-power-down mode and back-drive protection
• Latch-up performance exceeds 100mA per JESD 78, class II
• Green product and no Sb/Br

The SN74LVC1G332DBVR is a single 3-input positive-OR Gate. The device performs the Boolean function in Y = A + B + C or (A\ • B\ • C\)\ positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• ±24mA Output drive at 3.3V
• 10µA Maximum ICC low power consumption
• Inputs accept voltages to 5.5V
• Maximum tpd of 4.5ns at 3.3V
• Ioff supports live insertion, partial power down mode and back drive protection
• Supports down translation to VCC
• ESD protection exceeds JESD 22
• Latch-up performance exceeds 100mA per JESD 78, Class II
• Green product and no Sb/Br

The SN74LVC1G74DCTR is a single positive-edge-triggered D-type Flip-flop is designed for 1.65 to 5.5V VCC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Supports down translation to VCC
• ±24mA Output drive at 3.3V
• Ioff Supports live insertion, partial-power-down mode and back-drive protection
• Latch-up performance exceeds 100mA per JESD 78, class II
• Green product and no Sb/Br